Behavioral synthesis of property specification language (PSL) assertions

Outline:

H. Obereder, M. Pfaff, C. Saminger - Behavioral synthesis of property specification language (PSL) assertions - Proceedings of the International Symposium on Rapid System Prototyping 2007, Porto Alegre, Brasilien, 2007

Abstract:

In recent years more and more system designers discovered the importance of Assertion Based Verification (ABV) in coverage driven, functional simulations to keep pace with ever-increasing complexity of modern systems on chip (SoC). Using assertions plays a central role in the design-for-verification (DFV) methodology which is widely used in the industry. This paper presents a method that enables the major advantages of ABV beyond the borders of synthesis. By the use of the Property Specification Language (PSL) a way for the behavioral synthesis of properties will be shown. Furthermore the paper explains the integrated simulation of these hardware assertions by the aid of a hardware accelerator and cosimulator. Overall, the presented approach can decrease the time to market while raising the quality for complex SoCs at the same time.