DI (FH) Rainer Findenig
| Telefon: | +43 (0)50804-22426 |
| Fax: | +43 (0)50804-22499 |
| E-Mail: | rainer.findenig@fh-hagenberg.at |
Forschungseinheiten:
Publikationen:
| 2011 | Consistent SystemC and VHDL Code Generation from State Charts for Virtual Prototyping and RTL Synthesis R. Findenig, T. Leitner, V. Esen, W. Ecker - Consistent SystemC and VHDL Code Generation from State Charts for Virtual Prototyping and RTL Synthesis - Proceedings of DVCon 2011, San Jose, CA, Vereinigte Staaten von Amerika, 2011 |
| 2011 | Comparison of TLM2-Quantum Keeping and TLM+-Resource Modeling with Regard to Timing in Virtual Prototypes W. Ecker, V. Esen, R. Findenig, T. Leitner, M. Velten - Comparison of TLM2-Quantum Keeping and TLM+-Resource Modeling with Regard to Timing in Virtual Prototypes - Proceedings of DVCon 2011, San Jose, CA, Vereinigte Staaten von Amerika, 2011 |
| 2010 | State Chart Refinement Validation from Approximately Timed to Cycle Callable Models R. Findenig, W. Ecker - State Chart Refinement Validation from Approximately Timed to Cycle Callable Models - Proc. 2010 International Symposium on System-on-Chip, Tampere, Finnland, 2010, pp. 72-75 |
| 2010 | Transaction-Level State Charts in UML and SystemC with Zero-Time Evaluation R. Findenig, T. Leitner, M. Velten, W. Ecker - Transaction-Level State Charts in UML and SystemC with Zero-Time Evaluation - Proceedings of DVCon 2010, San Jose, CA, Vereinigte Staaten von Amerika, 2010, pp. 13-19 |
| 2010 | Fast and accurate UML State Chart modeling using TLM+ control flow abstraction R. Findenig, T. Leitner, M. Velten, W. Ecker - Fast and accurate UML State Chart modeling using TLM+ control flow abstraction - High Level Design Validation and Test Workshop (HLDVT) 2010, Anaheim, Vereinigte Staaten von Amerika, 2010, pp. 97-102 |
| 2010 | Model reduction techniques for the formal verification of hardware dependent software W. Ecker, V. Esen, R. Findenig, T. Steininger, M. Velten - Model reduction techniques for the formal verification of hardware dependent software - High Level Design Validation and Test Workshop (HLDVT) 2010, Anaheim, Vereinigte Staaten von Amerika, 2010, pp. 148-153 |
| 2009 | Optimizing the Hardware Usage of Parallel FSMs R. Findenig, F. Eibensteiner, M. Pfaff - Optimizing the Hardware Usage of Parallel FSMs - Proceedings of International Conference Computer Aided Systems Theory EUROCAST 2009, Las Palmas, Spanien, 2009, pp. 63-68 |
| 2009 | SynPSL: Behavioral Synthesis of PSL Assertions F. Eibensteiner, R. Findenig, M. Pfaff - SynPSL: Behavioral Synthesis of PSL Assertions - Proceedings of International Conference Computer Aided Systems Theory EUROCAST 2009, Las Palmas, Spanien, 2009, pp. 69-74 |
| 2009 | RAM basiertes Entwurfskonzept für flächenoptimierte Multi-IP-Core-Designs M. Hofstätter, G. Mayer, R. Findenig, F. Eibensteiner, M. Pfaff - RAM basiertes Entwurfskonzept für flächenoptimierte Multi-IP-Core-Designs - 3. Forschungsforum der Österreichischen Fachhochschulen, Villach, Österreich, 2009, pp. 147-151 |
| 2009 | Vergleich skalierbarer Softcore-Prozessoren hinsichtlich Rechenleistung und Chipfläche F. Pöschl, F. Eibensteiner, M. Bogner, R. Findenig - Vergleich skalierbarer Softcore-Prozessoren hinsichtlich Rechenleistung und Chipfläche - 3. Forschungsforum der Österreichischen Fachhochschulen, Villach, Österreich, 2009, pp. 152-157 |
| 2009 | A SystemC Design Pattern for the Cosimulation of Transaction-Level and Refined Cycle-Callable Models R. Findenig, W. Ecker - A SystemC Design Pattern for the Cosimulation of Transaction-Level and Refined Cycle-Callable Models - Proceedings Austrochip 2009, Graz, Österreich, 2009, pp. 123-128 |
| 2008 | Echtzeit-Überwachung von Hard- und Software mit PSL R. Findenig, F. Eibensteiner, M. Pfaff - Echtzeit-Überwachung von Hard- und Software mit PSL - Proceedings Austrochip 2008, Linz, Österreich, 2008, pp. 44-47 |
| 2007 | Effiziente Hardware-Abbildung von PSL-Assertions R. Findenig, M. Pfaff, F. Eibensteiner, J. Langer - Effiziente Hardware-Abbildung von PSL-Assertions - Tagungsband Austrochip 2007, Graz, Österreich, 2007, pp. 85-90 |
| 2007 | Embedded Robotic Solution: Integrating Robotics Interfaces with a High-Level CPU in a System-on-a-Chip F. Eibensteiner, R. Findenig, M. Pfaff, J. Langer, J. Tossold, W. Kubinger - Embedded Robotic Solution: Integrating Robotics Interfaces with a High-Level CPU in a System-on-a-Chip - Proceedings of International Conference Computer Aided Systems Theory EUROCAST 2007, Las Palmas, Spanien, 2007, pp. 1017-1024 |
